A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. One or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In many hardware applications, such as, graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate. In many computer system architectures of today, the majority of the above mentioned subsystems reside on the computer system's expansion bus.
The expansion bus is generally used as a method of adding functional components to the computer system. The functional components are physically coupled to the expansion bus, and use the expansion bus to communicate and exchange information. Dedicated bus-based designs (designs specifically conceived to operate from an expansion bus) typically embody the functional components. The peripheral component interconnect (PCI) bus is the expansion bus architecture upon which many dedicated bus-based designs are conceived. The PCI bus and its accompanying specification is an industry standardized, widely known, and widely supported expansion bus architecture.
Prior art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory bus 110, respectively. A PCI bus 112 is coupled to each of PCI agents 114, 116, 118, 120, 122, 124 respectively, and is additionally coupled to arbiter 106.
Referring still to prior art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, e.g., interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates a transaction (e.g., data transfer) with a "target device" or destination device (e.g., main memory 104). The PCI agent granted PCI bus ownership is referred to as the "initiator device" or simply, the initiator.
Prior art FIG. 2 shows an exemplary PCI agent 120 of PCI bus architecture 100. PCI agent 120 includes a device functional block 201 coupled to a bus interface unit 202. The bus interface unit is, in turn, coupled via connector 203 to the PCI bus 112. The bus interface unit (BIU) 202 manages the signals and protocols which comprises the PCI specification and describe how PCI agents use a PCI bus. The device functional block (DFB) 201 actualizes the function or functions PCI agent 120 is designed to accomplish (in this case, an audio device). DFB 201 includes the memory components, amplifiers, output drivers, and the like, required to implement the designed function. DFB 201 relies upon the BIU 202 to access PCI bus 112. The connector 203 couples the BIU 202 to the PCI bus 112. In so doing, the connector 203, and thus PCI agent 200, occupy one of the number of PCI slots of PCI bus 112.
The BIU 202, in order to properly interface DFB 201 with PCI bus 112, implements the functions and protocols defined in the PCI bus specification. BIU 202 also complies with all the rules governing communication across PCI bus 112. The PCI bus specification is relatively complex and timing wise aggressive in comparison to prior bus specifications. As such, designing a new DFB and a new corresponding BIU which will function correctly in a PCI bus environment is a non-trivial task. For example, the unique requirements of DFB 201, i.e., unique configuration requirements, device specific initiator requirements, and target requirements, need to be accounted for by BIU 202 in order to properly interface with PCI bus 112. In the same manner, DFB 201 is typically designed with the performance characteristics and limitations of the PCI specification, and as such, the BIU 202, in mind in order to ease the task of designing an adequate BIU. This facilitates the combining of the two functions, the BIU 202 and the DFB 201, into a single cohesive design. Because of this mutual dependence, the line between the BIU and the DFB is often blurred. The design of one unit becomes very much intertwined with and dependent upon the design of the other.
There is a problem, however, in the fact that a typical PCI bus (e.g., PCI bus 112) can usually support only a limited number of PCI agents. Once the limited number of PCI bus slots are occupied, it becomes expensive to add new PCI agents. If more PCI agents are desired, a hierarchical bridge to a subordinate PCI bus, which will accommodate its own set of PCI agents, is typically incorporated. The disadvantages of this solution include the added expense of the chipset implementing the PCI-to-PCI bridge function and the bus transfer latencies added to the PCI agents on the subordinate bus. Many manufacturers have turned to systems and methods for sharing a single one of the limited number of PCI bus slots among multiple PCI agents. Such systems and methods combined multiple PCI agents, or more particularly, the functions embodied by the PCI agents, into a single multi-agent device.
Prior art FIG. 3 shows one prior art multi-agent device 300 sharing a single PCI slot among multiple pre-existing PCI agents. Device 300 includes a plurality of DFBs 301, 302, and 303 (hereafter DFBs 301-303). Each of DFBs 301-303 are coupled to a common BIU 304. The common BIU 304 is coupled to PCI bus 112 via bus connector 305, thus occupying one of the limited number of PCI bus slots of PCI bus 112. Device 300 combines a number of DFBs into a single multi-agent device 300. Each of DFBs 301-303 share the common BIU 304. Many manufacturers take advantage of the rapid progress of integrated circuit technology and integrate multi-agent device 300 into a single semiconductor die.
The DFBs 301-303 need to adequately interface with the PCI bus 112 and comply with the PCI specification in order to function properly. The common BIU 304 performs the necessary interfacing with PCI bus 112 such that each of DFBs 301-303 are able to access the PCI bus 112. As such, common BIU 304 should be designed from the beginning with multiple agent support in mind. Where a BIU supports a single DFB, as described in the discussion of FIG. 2, the design of the BIU is tailored to the specific requirements of the single DFB. Where a BIU supports multiple DFBs, however, the task of designing a common BIU, which properly interfaces the multiple DFBs, becomes more complex. Such a BIU needs to support multiple DFBs, and thus, the design of the BIU needs to be tailored to the specific requirements of the multiple DFBs. Instead of designing to interface a single DFB and its particular requirements (as in FIG. 2), the common BIU 304 is designed to interface each of the multiple DFBs 301-303 and each of their particular requirements. If an additional number of DFBs are added, the complex common BIU 304 typically needs to be tailored for each additional DFB added to the multi-agent device 300. The complex common BIU 304 makes extension, or increasing the number of DFBs built into multi-agent device 300, more difficult.
To make the task of tailoring the common BIU more manageable, each of the DFBs 301-303 are designed to interface with the complex common BIU 304. This ensures compatibility with the common BIU 304, and eases the task of integrating the DFBs and the common BIU 304 into a single, functioning, bug-free, multi-agent device 300. By designing the DFBs 301-303 to interface with the complex BIU 304, however, a significant portion of design resources which could be used to design each of the DFBs 301-303 is spent ensuring each of the DFBs 301-303 will interface properly with the complex, common BIU 304.
Designing each of DFBs 301-303 to interface with common BIU 304 consumes significantly more time and effort than designing a DFB to interface with its own dedicated, relatively simple, BIU. Some prior art systems simply combine a number of BIU-DFB devices into a single integrated device, where each DFB comprising the device includes a dedicated BIU. Such integrated solutions essentially duplicate the PCI bus functions "on-chip." When combining existing designs into a single multi-agent (or more particularly, multi-block) device, such a solution is workable. When designing a new system, however, such a solution is inefficient and wasteful. Fabricating a separate BIU for each on-chip DFB is wasteful. Fabricating a majority of the PCI bus functions on-chip is wasteful. Where a design objective for a new system is efficiency, separate dedicated BIUs and complex on-chip PCI bus systems are not desired.
Thus, what is desired is a system for combining multiple functional blocks into a single integrated circuit in an efficient manner. Such a system should be easily extensible and should be capable of supporting a large number of on-chip functional blocks. Many multi-block devices are combinations of existing functional blocks, which vary little, if at all, between successive generations. Thus, what is further desired is a system which facilitates the efficient reuse of existing designs, requiring minimal custom tailoring of functional blocks in order to integrate them into a single multi-block system, and permits rapid design and fabrication of new multi-block devices. The method and system of the present invention satisfies the above needs.